S. Okhonin, M. Nagoga, J. M. Sallese and P. Fazan from the Ecole Polytechnique Fédérale de Lausanne (Preprint and Presentation at the IEEE SOI Conference, ISS/EPFL 2001) have proposed an embodiment of DRAM cells in the sub-100 nm range in which the memory cell is arranged as transistor structure in the body silicon layer of an SOI substrate. This concept dispenses with a formation of a capacitor that is specially provided for each cell. The semiconductor material which comprises the source region, the channel region and the drain region is in this case enclosed on all sides by SiO2 as electrically insulating material. A channel region that is not connected to a defined potential is thus present, which channel region, during operation of the cell, forms a zone that is fully or at least partially depleted of charge carriers (partially to fully depleted floating body). A gate electrode isolated from the channel region by a gate dielectric is situated on the top side.
The MOS transistor structure formed in this way is suitable for storing the charge which represents one bit. Disadvantages of this embodiment are the use of a comparatively expensive SOI substrate and the necessary compromise between a small space requirement sought for the cell and the gate length that can be realized.